(1) Field of the Invention
The invention relates to the manufacturing of semiconductor devices and more specifically to the manufacturing of CMOS image sensors.
(2) Description of the Prior Art
An image sensor is used to convert an optical image focused on the sensor into electrical signals. U.S. Pat. No. 5,461,425 teaches that the image sensor typically includes an array of light detecting elements, where each element produces a signal corresponding to the intensity of light impinging on that element when an image is focused on the array. These signals may then be used, for example, to display a corresponding image on a monitor or otherwise used to provide information about the optical image.
One very common type of image sensor is a charge-coupled device (CCD). Integrated circuit chips containing a CCD image sensor have a relatively low yield and are expensive due to the specialized processing involved. The CCD's also consume a relatively large amount of power.
U.S. Pat. No. 5,461,425 further teaches that a much less expensive type of image sensor is formed as an integrated circuit using a CMOS process. In such a CMOS type image sensor, a photodiode or phototransistor (or other suitable device) is used as the light-detecting element, where the conductivity of the element corresponds to the intensity of light impinging on the element. The variable signal thus generated by the light detecting element is an analog signal whose magnitude is approximately proportional (within a certain range) to the amount of light impinging on the element.
It is known to form these light-detecting elements in a two-dimensional core array which is addressable by row and column. Once a row of elements has been addressed, the analog signals from each of the light detecting elements in the row are coupled to the respective columns in the array.
An analog-to-digital (AID) converter may then be used to convert the analog signals on the columns to digital signals so as to provide only digital signals at the output of the image sensor chip.
What is needed is an inexpensive, but highly efficient, image sensor, which produces reliable images. Implied in this is that leakage current in the spacer region within the image sensor is reduced to a minimum. The present invention addresses the reduction in damage to the substrate surface and, with that, a reduction of the leakage current in the spacer region.
FIG. 1 shows a Prior Art gate electrode with the etching of the spacer, as follows:
FIG. 1a shows the poly silicon gate electrode 10, a layer 12 of tetra-ethyl-ortho-silicate (TEOS) has been deposited over the gate electrode 10 and the top surface of substrate 14. FIG. 1a shows that only one layer of the dielectric TEOS is deposited in order to form the gate electrode spacers.
FIG. 1b shows the results of the spacer etch, gate electrode spacers 16 are formed after etching has been completed. It is apparent from FIG. 1b that lack in control of the etching or over-etching can readily cause damage the surface areas 18 of substrate 14.
Using current fabrication technology, it is well known that defects in the substrate cause leakage current between the gate electrodes of the image sensor, especially where the substrate defects are caused by plasma damage. It is therefore of key importance to produce a substrate surface that is free of damage and, more particularly, to be able to perform spacer etching without causing damage to the substrate surface. Current practice uses a single layer of dielectric above the spacer between the gate electrodes of the image sensor. With only a single layer of dielectric, it is difficult to sense and control the etch stop above the substrate. This difficulty in controlling the etching process results in substrate surface damage; this in turn results in leakage current between the gate electrodes of the CMOS image sensor device.
An additional problem is that, during the growth of field oxide, a phenomenon occurs that causes defects when the gate oxide is grown. This problem is referred to as white ribbon or white pixels. A thin layer of silicon nitride can form on the silicon surface (i.e., the pad-oxide/silicon surface interface) as a result of the reaction of NH.sub.3 and silicon at that interface. When the gate oxide is grown, the growth rate becomes impeded at the locations where the silicon nitride has been formed. The gate oxide is thus thinner at these locations than elsewhere, causing low-voltage breakdown of the gate oxide.
U.S. Pat. No. 5,702,972 (Tsai et al.) U.S. Pat. No. 5,747,373 (Yu) and U.S. Pat. No. 5,763,312 (Jeng et al.) show SiN/Ox double spacers.
U.S. Pat. No. 5,747,373 (Yu) shows an oxide/SiN double spacer.
U.S. Pat. No. 5,461,425 (Fowler et al.) shows a CMOS image sensor.